So far, inverter circuits that use transistors such as bipolar transistors and field effect transistors (FETs) have been widely used. In FIG. 36a, a typical example of an existing CMOS inverter circuit that uses MOSFETs as transistors is shown. A CMOS inverter circuit 200 has a PMOSFET 201 having a threshold voltage VTHP and an NMOSFET 202 having a threshold voltage VTHN with these FETs serially connected between a high level power supply potential VDD and a low level power supply potential VSS (normally VTHP is negative and VTN is positive). A source of the PMOSFET 201 is connected to the high level power supply potential VDD and a source of the NMOSFET 202 is connected to the low level power supply potential VSS. Drains of both of the MOSFETs 201 and 202 are connected to each other and a connection point N (node) thereof is connected to an output terminal OUT. Furthermore, both gates of the MOSFETs 201 and 202 are connected to an input terminal IN to which an input signal that oscillates between a high level input potential VINH and a low level input potential VINL is inputted. In the present specification, unless stated, “connection” of a circuit element means “electrical connection”.
An ordinary operation of the CMOS inverter circuit 200 having such a configuration is shown in FIG. 36b and FIG. 36c. In FIGS. 36b and 36c, in order to show an ON/OFF state of the MOSFETs 201 and 202, the MOSFETs 201 and 202 each is shown with a sign of a switch. As shown in FIG. 36b, when to the input terminal IN, a high level input potential VINH equal to or higher than a value obtained by subtracting an absolute value of the threshold voltage of the PMOSFET |VTHP| from the high level power supply potential VDD is inputted, the PMOSFET 201 is turned off and the NMOSFET 202 is turned on to supply a potential substantially equal to the low level power supply potential VSS to the output terminal OUT as an output signal. Furthermore, as shown in FIG. 36c, when to the input terminal IN, a low level input potential VINL equal to or lower than a value obtained by adding an absolute value of the threshold voltage of the NMOSFET |VTHN| to the low level power supply potential VSS is inputted, the PMOSFET 201 is turned on and the NMOSFET 202 is turned off to supply a potential substantially equal to the high level power supply potential VDD to the output terminal OUT as an output signal.
However, in the case of an input signal being supplied from, for instance, an IC and so on of which operating voltage is low, problems below are caused. As shown in FIG. 37a, in the case of a high level input potential VINH inputted to the input terminal IN being smaller than a value obtained by subtracting an absolute value of the threshold voltage of the PMOSFET 201 |VTHP| from the high level power supply potential VDD, in the PMOSFET 201, a gate-source voltage VGS (=gate potential VG−source potential VS)<−|VTHP| is realized, the PMOSFET 201 is not turned off. As a result, both the MOSFETs 201 and 202 are turned on, and a potential divided by on-state resistances of the PMOSFET 201 and the NMOSFET 202 is outputted to the output terminal OUT, that is, the low level power supply potential VSS is not outputted. Similarly, in the case of a low level input potential VINL inputted to the input terminal IN being higher than a value obtained by adding an absolute value of the threshold voltage of the NMOSFET 202 |VTHN| to the low level power supply potential VSS, the NMOSFET 202 is not turned off, both the MOSFETs 201 and 202 are turned on, and the high level power supply potential VDD is not outputted to the output terminal OUT. Thus, in the case of, because of levels between input potentials VINH, VINL and power supply potentials VDD, VSS being different, the MOSFETs 201 and 202 of the inverter circuit 200 being not assuredly turned on or off and an output not taking a desired value, there are problems in that a circuit in a later stage of the inverter 200 cannot be driven, or an operation of such circuit becomes uncertain. Furthermore, since both the MOSFETs 201 and 202 are simultaneously turned on to flow a short current, there is caused a problem also in that power consumption increases.
In order to overcome the problems as mentioned above, it is proposed that, in a level shifter circuit that has a first input inverter and a second output inverter, a DC level of a signal that is inputted from the first inverter to the second inverter is convened by use of a capacitor (condenser) and a biasing means (see Japanese Patent Application Laid-Open No. H9-172367). However, in this circuit, since a DC level converting capacitor that is connected between a gate of each of the transistors constituting the second inverter and an output of the first inverter is always connected to a high level power supply potential or a low level power supply potential with the biasing means, there are problems in that charge and discharge of the capacitors may adversely affect on the dynamic characteristics of the circuit (that is, lower a circuit operation speed), or power consumption due to the charge and discharge of the capacitors may become a magnitude that cannot be ignored. Furthermore, in the case of there being variations in the threshold voltages of the transistors, the electrostatic capacity of each of the capacitors can be conformed with difficulty to a corresponding transistor. Accordingly, there may occur a problem in that a voltage between both ends of the DC level converting capacitor cannot be matched to a threshold voltage of the corresponding transistor, and the transistors cannot be accurately turned on or off.
Furthermore, in the inverter circuit 200 shown in FIG. 36a, in the case of a power supply voltage (VDD-VSS) being small, for instance, to suppress the power consumption, and, being not sufficiently large to the absolute values of the threshold voltages of the MOSFETs 201 and 202, even when an amplitude of an input signal inputted to the input terminal IN is equal to that of a power supply voltage, there may occur a problem in that a sufficient current cannot be flowed to the MOSFETs 201 and 202 to drive with high speed. This is due to that it is not a gate-source voltage VGS that contributes to a current that flows in the MOSFET but VGS-VTH. For instance, in the inverter circuit 200 shown in FIG. 36a, VDD=3.3 V, VSS=0 V (ground), a threshold voltage of the PMOSFET 201 VTHP=−2 V, a threshold voltage of the NMOSFET 202 VTHN=3 V, a high level input potential VINH=VDD=3.3 V, and a low level input potential VINL=VSS=0 V are assumed. In the case of the low level input potential VINL being added to the input terminal IN, in the PMOSFET 201. VGS−VTHP=−3.3−(−2)=−1.3 V is satisfied, and the PMOSFET 201 is thus turned on, whereas in the NMOSFET 202, VGS−VTHP=0−3=−3 V is satisfied, and the NMOSFET 202 is thus turned off. In this case, since the absolute value of the threshold voltage (−2 V) of the PMOSFET is sufficiently small with respect to a power supply voltage (that is, an amplitude of an input signal), the absolute value of (VGS−VTHP) can be taken large (1.3 V), accordingly, there is caused no problem. On the other hand, in the case of a high level input potential VINH being added to the input terminal IN, in the PMOSFET 201, VGS−VTHP=0−(−2)=2 V is satisfied, and the PMOSFET 201 is thus turned off, whereas in the NMOSFET 202, VGS−VTHP=3.3−3=0.3 V is satisfied, and the NMOSFET 202 is thus turned on. However, since VGS−VTHP is such small as 0.3 V, a small current flows and the NMOSFET 202 cannot be operated (on) with high speed. It is a matter of course that when amplitudes of the power supply voltage and the input signal are made larger, the high-speed operation can be realized, but the power consumption increases.